A typical integrated circuit contains a plurality of metal pathways that provide electrical power to the various semiconductor devices forming the integrated circuit, and that allow these semiconductor devices to share/exchange electrical information. Within integrated circuits, metal layers are stacked on top of one another by using intermetal or “interlayer” dielectrics that insulate the metal layers from each other.
Generally, each metal layer must form electrical contact to at least one additional metal layer. Such metal-layer-to-metal-layer electrical contact is achieved by etching a hole (i.e., a via) in the interlayer dielectric that separates the metal layers, and by filling the resulting via with a metal to create an interconnect as described further below. Metal layers typically occupy etched pathways or “lines” in the interlayer dielectric. For simplicity, as used herein, the term “via” refers to any feature such as a hole, line or other similar feature formed within a dielectric layer that assists in establishing an electrical connection through the dielectric layer to a conductive layer underlying the dielectric layer.
Because copper has a lower resistivity than aluminum, copper metals layers and interconnects have gained popularity in contrast to more conventional aluminum metal layers and interconnects. Copper atoms, however, are highly mobile in silicon dioxide and may create electrical defects in silicon. Accordingly, copper metal layers and copper interconnect vias conventionally are encapsulated with a barrier material (e.g., to prevent copper atoms from creating leakage paths in silicon dioxide or similar interlayers and/or defects in the silicon substrate on which the copper layers and interconnects are formed).
Barrier layers typically are deposited on via sidewalls and bottoms prior to copper seed layer deposition, and may include materials such as tungsten, titanium, tantalum, nitrides thereof, etc. Tantalum nitride is particularly popular due its lower resistivity and favorable adhesion properties.
As is well known, an increase in device performance is typically accompanied by a decrease in device area or an increase in device density. An increase in device density requires a decrease in the via dimensions used to form interconnects (e.g., a larger depth-to-width ratio or a larger “aspect ratio”). As via dimensions decrease, and aspect ratios increase, forming adequately thick and uniform barrier layers on the sidewalls of vias has become difficult. This problem is exacerbated within low K dielectric interlayers, as sidewall barrier layers often serve the additional role of providing mechanical strength to such low K dielectric interlayers.
Accordingly, a need exists for improved methods and apparatus for forming barrier layers in high aspect ratio vias.